CD54HC195 register equivalent, 4-bit parallel access register.
Description
* Asynchronous Master Reset
* J, K, (D) Inputs to First Stage
* Fully Synchronous Serial or Parallel Data Transfer
* Shift Right and Paralle.
It performs serial, parallel, serial to parallel, or parallel to serial data transfers at very high speeds.
The two mod.
* Asynchronous Master Reset
* J, K, (D) Inputs to First Stage
* Fully Synchronous Serial or Parallel Data Transfer
* Shift Right and Parallel Load Capability
* Complementary Output From Last Stage
* Buffered Inputs
* CTyL.
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